TSL3301CL【PDF 7/21 页】IC LINEAR SENSOR ARRAY 8CHIPLED

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TSL3301CL

102 ?1 LINEAR OPTICAL SENSOR ARRAY

WITH ANALOG-TO-DIGITAL CONVERTER

TAOS141 JULY 2011

The LUMENOLOGY r Company

www.taosinc.com

PROGRAMMING INFORMATION

A minimum of 5 clock cycles after the stop bit is required after any command to ensure that the internal logic

actions have been completed.

Reset Commands

Reset commands are used to put the TSL3301CL into a known state.

IRESET Interface Initialization

Encoding: Break Character (10 or more consecutive start bits, or zeros)

The commands vary in length from one to three bytes. IRESET initializes the internal state machine that keeps

track of which command bytes have been received. This command should be first and given only once after

power-up to synchronize the TSL3301CL internal command interpreter.

An alternative is to issue three successive RESET commands.

RESET Main Reset

Encoding: 0x1b: <0001_1011>

RESET resets most of the internal control logic of the TSL3301CL and any READPixel command currently in

progress is aborted. RESET puts the pixel integrators into the auto-zero/reset state. Any values that were being

held in the arrays sample/hold circuits are lost.

NOTE:

The value on the SDOUT pin is not guaranteed from the time power is applied until 30 clocks after

the first RESET command is issued.

Pixel Action Commands

Pixel action commands allow the user to control pixel integration and reading of pixel data.

STARTInt Start Integration

Encoding: 0x08: <0000_1000>

STARTInt causes each pixel to leave the reset state and to start integrating light. The actual execution

of STARTInt is delayed 22 clock cycles until the pixel reset cycle has been completed. (See imaging below.)

SAMPLEInt Stop Integration

Encoding: 0x10: <0001_0000>

SAMPLEInt causes each pixel to store its integrators contents into a sample and hold circuit. Also, the Integrator

is returned to the reset state.

READPixel Read Pixel Data

Encoding: 0x02: <0000_0010>

READPixel causes the sampled value of each pixel to be converted to an 8-bit digital value that is clocked out

on the SDOUT pin. The LSB is the first data bit, which is preceded by a START bit (logic 0) and followed by a

STOP bit (logic 1). Each pixel in the device is presented on SDOUT starting from pixel 00 and completes with

pixel 101. There is a 44-clock cycle delay from the completion of the READPixel command until the first pixel

data is output.

Gain and offset registers are used to adjust the ADC converter to maximize dynamic range and should be

programmed prior to invoking the READPixel command.

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